The present invention relates to applying a delay amount to an input signal to generate a delay signal, and more particularly, to a delay signal generating apparatus using a glitch free digitally controlled delay line and an associated delay signal generating method.
From a practical point of view, the digitally controlled delay line (DCDL) plays an important role in many applications such as all-digital phase locked loop (ADPLL), delay-locked loop (DLL), phase shifter, clock generator, etc. However, glitch is an unwanted pulse which occurs in a digital circuit, and becomes the most common design problem in the digital circuit. For example, the unwanted glitch may lead to loss of data. With regard to a typical DCDL, it may have glitch under the presence of a delay control code switching. Thus, there is a need for an innovative DCDL design which is glitch free.